Specifies the cache eviction level to be used by the compiler for streaming loads and stores. This option only applies to Intel® MIC Architecture.
Arguments
Description
This option specifies the cache eviction (clevict) level to be used by the compiler for streaming loads and stores.
Depending on the level used, the compiler will generate clevict0 and/or clevict1 instructions that evict the cache-line (corresponding to the load or the store) from the first-level and second-level caches. These cache eviction instructions will be generated after performing the corresponding load/store operation.
For more information on how to mark loads/stores as streaming, see the description of the vector nontemporal pragma.
Parent topic: Advanced Optimization Options
See Also
opt-threads-per-core, Qopt-threads-per-core compiler option
opt-streaming-stores, Qopt-streaming-stores compiler option
vector nontemporal pragma
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